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EP1K100QC208-3N

EP1K100QC208-3N资料
EP1K100QC208-3N
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Manufacturer:ALT
Description:NOTES: 2. When the differential input voltage (VI+ C VIC) is less than or equal to 0 V, the output code is 0000 0000.   3. The internal reference voltage is equal to the voltage applied to REF/2 or approximately equal to one-half of the VCC when REF/2   is left open. The voltage at REF/2 should be one-half the full-scale differential input voltage between the analog inputs. Thus, the   differential input voltage range when REF/2 is open and VCC = 5 V is 0 V to 5 V. VREF/2 for an input voltage range from 0.5 V to 3.5 V   (full-scale differential voltage of 3 V) is 1.5 V.   4. These values are with respect to DGTL GND.   5. Total unadjusted error is specified only at an fclock of 640 kHz with a duty cycle of 40% to 60% (pulse duration 625 ns to 937 ns).   For frequencies above this limit or pulse duration below 625 ns, error may increase. The duty cycle limits should be observed for   an fclock greater than 640 kHz. Below 640 kHz, this duty cycle limit can be exceeded provided tw(CLK) remains within limits.
 
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型 号:EP1K100QC208-3N
厂 家:ALT
封 装:
批 号:(VBE5884
数 量:123
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