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| FFPF06U40DN资料 | |
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FFPF06U40DN PDF Download |
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File Size : 116 KB
Manufacturer:FAIR Description:• PLL clock distribution optimized for SSTL_2 DDR SDRAM applications. • Distributes one differential clock input pair to five differential clock output pairs. • Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 • Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 • External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input. • Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers • Available Package: C Plastic 28-pin TSSOP |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：FFPF06U40DN 厂 家：FAIR 封 装： 批 号： 数 量：2194 说 明：Bid Price |
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运 费： 所在地： 新旧程度： |
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| 联系人：刘先生，罗小姐， |
| 电 话：0086-755-83576094, |
| 手 机：0086-(0)13728684091 |
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| 传 真：86-755-83576061 |
| EMail：sales@xgf-ic.com, kupan_ic@126.com |
| 公司地址： 深圳市龙岗区龙城街道龙翔大道9009号珠江广场A2栋11F |
