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| IRFIBC20G资料 | |
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IRFIBC20G PDF Download |
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File Size : 116 KB
Manufacturer:IR/VISH Description:Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1380D/CY7C1382D operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：IRFIBC20G 厂 家：IR/VISH 封 装： 批 号：0621 数 量：291 说 明：Bid Price |
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运 费： 所在地： 新旧程度： |
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