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| MA2440资料 | |
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MA2440 PDF Download |
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File Size : 116 KB
Manufacturer:SHIN Description:Description Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1. Synchronous output enable. When nsOE is HIGH, nQ and nQ are synchronously stopped. OMODE selects whether the outputs are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ is stopped in a HIGH/LOW state, while the nQ is stopped at a LOW/HIGH state. When OMODE is LOW, the outputs are tri- stated. Set nsOE LOW for normal operation. Feedback clock output Complementary feedback clock output Clock outputs Complementary clock outputs Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) REF clock input or differential (LOW) REF clock input Sets the drive strength of the output drivers and feedback inputs to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or eHSTL/HSTL (LOW) compatible. Used in conjuction with VDDQ to set the interface levels. Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock (has internal pull-up). Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on each bank. (See Control Summary table.) |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：MA2440 厂 家：SHIN 封 装： 批 号： 数 量：149 说 明：Bid Price |
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运 费： 所在地： 新旧程度： |
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| 联系人：刘先生，罗小姐， |
| 电 话：0086-755-83576094, |
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