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| MMBT5401LT1G资料 | |
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MMBT5401LT1G PDF Download |
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File Size : 116 KB
Manufacturer:ONS Description:Most connections between the FPGA device and the Serial EEPROM are simple and self-explanatory: • The DATA output of the high-density AT17 Series drives DIN of the FPGA devices. • The master FPGA CCLK output drives the CLK input of the high-density AT17 Series. • The CEO output of any AT17C/LV512/010 drives the CE input of the next AT17C/LV512/010 in a cascade chain of PROMs. • SER_EN must be connected to VCC, (except during ISP). READY is available as an open-collector indicator of the devices RESET status; it is driven Low while the device is in its POWER-ON RESET cycle and released (tri-stated) when the cycle is complete. There are two different ways to use the inputs CE and OE, as shown in the AC Characteristics waveforms. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：MMBT5401LT1G 厂 家：ONS 封 装： 批 号：0639(MQ6 数 量：38541 说 明：Bid Price |
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运 费： 所在地： 新旧程度： |
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