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| MP1542DK-LF-Z资料 | |
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MP1542DK-LF-Z PDF Download |
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File Size : 116 KB
Manufacturer:MNPW Description: Specifications are not production tested but guaranteed by design and/or characterization data at initial product release. See Typical Performance Characteristics. 3Specifications before calibration. Channel system calibration reduces these errors to the order of the noise. 4Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error. 5ADC zero-scale self-calibration reduces this error to 10 mV. Channel zero-scale system calibration reduces this error to the order of the noise. 6For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for more details. 7The adjacent channels are not affected by AIN voltage up to 16.5 V. 8Pin impedance is from the pin to the internal node. In normal circuit configuration, the analog input total impedance is typically 108.5 kΩ + 15.5 kΩ = 124 kΩ. 9For specified performance. Part is functional with lower VREF. 10Dynamic current charging the sigma-delta modulator input switching capacitor. 11Outside the specified calibration range, calibration is possible but the performance may degrade. 12These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 13With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register). 14External MCLKIN = 0 V or DVDD, digital inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：MP1542DK-LF-Z 厂 家：MNPW 封 装： 批 号：8B307 数 量：50 说 明：Bid Price |
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运 费： 所在地： 新旧程度： |
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| 联系人：刘先生，罗小姐，刘小姐，刘先生，王先生 |
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