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| MSP-FET430P410资料 | |
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MSP-FET430P410 PDF Download |
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File Size : 116 KB
Manufacturer:TI Description: C Address translation unit C Some internal configuration registers accessible from PCI Two-channel integrated DMA controller (writes to ROM/Port X not supported) C Supports direct mode or chaining mode (automatic linking of DMA transfers) C Supports scatter gatheringRead or write discontinuous memory C Interrupt on completed segment, chain, and error C Local-to-local memory C PCI-to-PCI memory C PCI-to-local memory C PCI memory-to-local memory Message unit C Two doorbell registers C Two inbound and two outbound messaging registers C I2O message controller I2C controller with full master/slave support (except broadcast all) Programmable interrupt controller (PIC) C Five hardware interrupts (IRQs) or 16 serial interrupts C Four programmable timers Integrated PCI bus, CPU, and SDRAM clock generation Programmable PCI bus, 60x, and memory interface output drivers Dynamic power managementSupports 60x nap, doze, and sleep modes Programmable input and output signals with watchpoint capability Built-in PCI bus performance monitor facility Debug features C Memory attribute and PCI attribute signals C Debug address signals C MIV signalMarks valid address and data bus cycles on the memory bus C Error injection/capture on data path C IEEE 1149.1 (JTAG)/test interface Processor core interface High-performance, superscalar processor core Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit (LSU), system register unit (SRU), and a branch processing unit (BPU) 16-Kbyte instruction cache 16-Kbyte data cache Lockable L1 cache, entire cache or on a per-way basis |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：MSP-FET430P410 厂 家：TI 封 装： 批 号：07+ 数 量：1 说 明：Bid Price |
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运 费： 所在地： 新旧程度： |
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| 联系人：刘先生，罗小姐，刘小姐，刘先生，王先生 |
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